The majority of present day integrated circuits (ICs) are implemented by using a plurality of interconnected field effect transistors (FETs), which may be realized as metal oxide semiconductor field effect transistors (MOSFETs or MOS transistors). A MOSFET includes a gate electrode as a control electrode that is formed over a semiconductor substrate, and spaced-apart source and drain regions formed within the semiconductor substrate and between which a current can flow. The source and drain regions are typically accessed via respective conductive contacts formed on the source and drain regions. Bias voltages applied to the gate electrode, the source contact, and the drain contact control the flow of current through a channel in the semiconductor substrate between the source and drain regions beneath the gate electrode. Conductive metal interconnects (plugs) formed in an insulating layer are typically used to deliver bias voltages to the gate, source, and drain contacts.
In a MOSFET, capacitance is present between the conductive metal interconnects and the conductive portion of the gate stack. This undesired capacitance can adversely affect the performance of the MOSFET. This capacitance is roughly proportional to the height of the conductive gate stack. Accordingly, reducing the height of the gate structure has been identified as one of the most effective ways of reducing this capacitance. Unfortunately, the gate height has reached a scaling barrier due to the practical limitations and constraints of conventional semiconductor fabrication processes technologies.